Design-for-Testing or Design for Testability (“DFT”) refers to integrated circuit design techniques that add certain testability features to a hardware product design. The DFT features make it easier to develop and apply various manufacturing tests for the designed hardware. The purpose of manufacturing tests is to validate that the hardware products contain no manufacturing defects that could adversely affect the product's proper functioning.
Scan chain is one example of a technique implemented in a DFT process, which makes testing easier by providing a simple way to set and observe every latch in an integrated circuit (IC). The basic structure of a scan chain includes the following set of signals in order to control and observe the scan mechanism. Scan_In (SI) and Scan_Out(SO) are the input and output of a scan chain, respectively. A shift enable pin (SE) is a signal that is added to a design. When SE is asserted, every latch in the design is connected to a respective bit of a shift register. Another control pin called design-for-test bypass (DFTBYP) enables IC into “CAPTURE mode,” as SE is not asserted. A clock signal is used for controlling all the latches, or flip-flops, in the chain during testing of the IC. An arbitrary test pattern (for example, a vector of random 0's and 1's) can be entered into the chain of latches, and the state of every latch can be read out.
Test patterns (e.g., binary vectors) are applied as SI inputs to a DFT circuit. Additionally, functional clock signals (e.g., pulses) are sent to the DFT circuit for controlling and timing operation during a “CAPTURE mode,” as described in further detail below. The results of a scan test are then shifted out via chip output pins as SO outputs and compared against the expected results. Conventionally, application of scan techniques as described above demands a large amount of memory and test time, and produces large vector sets.